FSM Partitioning and Synthesis Targeting an Embedded Autonomous FSM

This paper concerns the synthesis of complex finite state machines (FSM) by a novel partitioning and encoding approach. The target architecture is a generalization of FSM implementations with embedded loadable counters. Starting with a subgraph extraction constraints driven partitioning generates three parts, a sequencing, a command and an autonomous logic block. By solving the encoding problem simultaneously for all blocks the total area of the partitioned circuits is minimized. Experimental results demonstrate the efficiency of the proposed approach.